1. Field
This patent document relates to a memory system and a memory module.
2. Description of the Related Art
In most cases, a single controller is used to control multiple memory devices.
As illustrated in FIG. 1A, when a control bus CMD/ADDR_BUS0 and a data bus DATA_BUS 0 between a controller 100 and a memory device 110_0 are separated from a control bus CMD/ADD_BUS1 and a data bus DATA_BUS1 between the controller 100 and a memory device 110_1, the controller 100 can separately control the memory devices 110_0 and 110_1. A command and address are transmitted through the control bus. For example, while the memory device 110_0 performs a read operation, the memory device 110_1 may perform a write operation.
As illustrated in FIG. 1B, when a control bus CMD/ADDR_BUS and a data bus DATA_BUS are shared by the memory devices 110_0 and 110_1, lines for transmitting signals CS0 and CS1 for distinguishing between the memory devices 110_0 and 110_1 are provided. The lines for transmitting the signals CS0 and CS1 among signals of the control bus CMD/ADDR_BUS are separately provided for the respective memory devices 110_0 and 110_1. In this case, a memory device selected by the signals CS0 and CS1 between the memory devices 110_0 and 110_1 may perform an operation in response to the command transferred through the control bus CMD/ADDR_BUS, and exchange signals with the controller 100 through the data bus DATA_BUS. The signals CS0 and CS1 are command signals transmitted to the control bus CMD/ADD_BUS, but are independently allocated to the memory devices 110_0 and 110_1 unlike the other common command signals transmitted through the control bus CMD/ADDR_BUS. Thus, the signals CS0 and CS1 are separately illustrated in FIG. 1B.
As the number of memory devices coupled to the controller increases, the number of lines required increases. This lead to increase difficulties in system design as well as increased manufacturing costs.